The semiconductor industry aims to manufacture integrated circuits with higher and higher densities of semiconductor devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to a continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as gate lengths in field-effect transistors and the width of conductive lines, is driven by lithographic performance.
With conventional photolithography systems, radiation is provided through or reflected off a mask or reticle to form an image on a semiconductor wafer. Generally, the image is focused on the wafer to expose and pattern a layer of material, such as photoresist material. In turn, the photoresist material is utilized to define doping regions, deposition regions, etching regions, or other structures and features in one or more layers of the semiconductor wafer. The photoresist material can also define conductive lines or conductive pads associated with metal layers of a semiconductor device. Further, the photoresist material can define isolation regions, transistor gates, or other transistor structures and elements.
A multiple exposure/pattern process, which utilizes two or more photolithographic sub-processes, can be used to form photoresist patterns of extremely small and tightly packed features. One type of double exposure process forms a first photoresist pattern, etches the wafer using the first photoresist pattern, subsequently forms a second photoresist pattern, and etches the wafer using the second photoresist pattern. Another type of double exposure process forms a first photoresist pattern, coats the first photoresist pattern with a second photoresist layer, exposes and develops the second photoresist layer, and then etches the wafer. This double exposure process is sometimes referred to as a double exposure single etch process.
Currently available photolithography tools used in the semiconductor industry can achieve line resolutions of about 80 nanometers. More specifically, 193 nanometer immersion stepper technology can achieve pitches as short as 80 nanometers on a single mask. In practice, device features having pitches below 80 nanometers can be achieved using double exposure/pattern processes as mentioned above. Unfortunately, even if multiple exposure procedures are used, downward scaling of pitch or line separation is ultimately limited by the practical performance capabilities of the photolithographic tools. Consequently, certain design rules are commonly used to check the viability and manufacturability of desired semiconductor device features. For example, design rule check (DRC) methodologies can be applied to identify potential tip-to-tip and/or tip-to-line violations in a proposed layout of conductive traces, such as local interconnects. Thus, if the proposed layout includes tip-to-tip or tip-to-line spacing that is too short for the particular photolithographic tool, then it may not be possible to fabricate devices using that proposed layout without shorting some conductive traces together.